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[Button control] 4yue11haoxiawu

Description: 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the software and hardware design development (VB or V C and C language), downloading software and download Plate 3, Player (using Visual Basic 6.0 design) can play multiple formats of music and movies, Photo View and so on four small small inductance capacitor tester
Platform: | Size: 16384 | Author: wangxing | Hits:

[VHDL-FPGA-Verilog] FIR31

Description: 设计一个线性相位FIR滤波器（31阶） 输入8位，输出8位,H(n)={1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69,111,128,111,……2,1} H(n)具有对称性。 输入信号范围 [±99，0，0，0， ±70，0，0，0， ±99，0，0，0， ±70，…]-Design a linear phase FIR filter (31 bands) 8 input, 8 output, H (n) = (1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69111128111, ... ... 2,1) H (n) has a symmetry. Input signal range [± 99,0,0,0, ± 70,0,0,0, ± 99,0,0,0, ± 70, ...]
Platform: | Size: 2641920 | Author: 陈金立 | Hits:

[Communication-Mobile] 2005612300003FIRVHDL

Description: 自己在一个通信项目中设计的滤波器，在传统设计的基础上作了改进，具有更好的特性。-himself in a communications projects designed filter, in the traditional design made on the basis of improvement has better features.
Platform: | Size: 26624 | Author: 小令 | Hits:

[VHDL-FPGA-Verilog] DSPBuilderFIR.files

Description: 在信息信号处理过程中，如对信号的过滤、检测、预测等，都要使用滤波器，数字滤波器是数字信号处理（DSP，DigitalSignalProcessing）中使用最广泛的一种器件。常用的滤波器有无限长单位脉冲响应（ⅡR）滤波器和有限长单位脉冲响应（FIR）滤波器两种[1]，其中，FIR滤波器能提供理想的线性相位响应，在整个频带上获得常数群时延从而得到零失真输出信号，同时它可以采用十分简单的算法实现，这两个优点使FIR滤波器成为明智的设计工程师的首选，在采用VHDL或VerilogHDL等硬件描述语言设计数字滤波器时，由于程序的编写往往不能达到良好优化而使滤波器性能表现一般。而采用调试好的IPCore需要向Altera公司购买。笔者采用了一种基于DSPBuilder的FPGA设计方法，使FIR滤波器设计较为简单易行，并能满足设计要求。-err
Platform: | Size: 96256 | Author: yaoming | Hits:

[Other] 66_FIR11

Description: VHDLfir滤波器资料 可以实际上 一落千丈-VHDLfir filter information can be actually nosedived
Platform: | Size: 7168 | Author: jinlong | Hits:

[VHDL-FPGA-Verilog] yl_cic32

Description: 一个三阶梳妆滤波器（CIC）的vhdl的源码-Dressing a third-order filter (CIC) of the VHDL source code
Platform: | Size: 1024 | Author: 白杨 | Hits:

[VHDL-FPGA-Verilog] FIR_verilog

Description: 基于verilog的FIR滤波器，有两种实现方法，分别给出仿真波形-Verilog based on the FIR filter, there are two methods, respectively, the simulation waveform
Platform: | Size: 628736 | Author: yejianchao | Hits:

[VHDL-FPGA-Verilog] fir_fpga

Description: 通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role
Platform: | Size: 2135040 | Author: fdf | Hits:

[VHDL-FPGA-Verilog] 6tapFIR

Description: 6阶FIR+verliog+分布式算法（DA）-6 bands FIR+ Verliog+ Distributed Arithmetic (DA)
Platform: | Size: 2048 | Author: zs | Hits:

[VHDL-FPGA-Verilog] fir_Verilog

Description: 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
Platform: | Size: 5120 | Author: yuming | Hits:

[Software Engineering] bandpass-filter

Description: 这是一篇关于带通滤波器的毕业设计论文，涵盖IIR与FIR滤波器的设计！-This is an article on the band-pass filter design graduate thesis, covering IIR and FIR filter design!
Platform: | Size: 1155072 | Author: yuming | Hits:

[OS Develop] dds

Description: 这是一个用vhdl语言实现dds的例子，已在quartusII里调通并可以下载到实验箱上，功能正确-This is a use of VHDL language dds example, has been in tune quartusII pass and can be downloaded to the experimental box, the function correctly
Platform: | Size: 331776 | Author: leezhihui | Hits:

[VHDL-FPGA-Verilog] iir

Description: 数字信号处理的fpga实现，用VHDL语言编程实现IIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve IIR filter
Platform: | Size: 1024 | Author: songjunmin | Hits:

[DSP program] fir_gen

Description: 数字信号处理的fpga实现，用VHDL语言编程实现FIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve FIR filter
Platform: | Size: 1024 | Author: songjunmin | Hits:

[VHDL-FPGA-Verilog] sdram_vhd

Description: FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
Platform: | Size: 2186240 | Author: yuhl | Hits:

[VHDL-FPGA-Verilog] coeff_rom_1_6

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] coeff_rom_2_5

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[Communication-Mobile] ruan

Description: 扩频发射机，信道编码采用(2, 1, 7)卷积 码, 扩频模块采用扩频长度255 的kasami码, 极性变换模块为3bit 量化模式, 内插模块为每两比特间插入7bit 和输出滤波为16 阶的FIR 滤波器。-direct sequence spread spectrum transmitter
Platform: | Size: 1024 | Author: 靳超 | Hits:

[Other] coe

Description: 自动计算fir滤波器系数的工具，不妨一试-Automatic calculation of filter coefficients fir tools, try
Platform: | Size: 27648 | Author: sumli | Hits:

[Other] fir_16

Description: vhdl代码 实现16阶fir滤波器，可以仿真通过-vhdl code fir filter stage 16 can be adopted simulation
Platform: | Size: 3072 | Author: sumli | Hits:
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